Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation
نویسندگان
چکیده
منابع مشابه
Bit-serial Parallel Processing Vlsi Architecture for a Block Matching Motion Estimation Algorithm
Motion estimation is a key element in video signal interframe coding systems. Among the different techniques proposed for the estimation of movement of pixels between two successive frames, full-search block-matching algorithms (FSBMA) are more attractive due to their low mathematical complexity. The FSBMA based on the mean absolute difference (MAD) criterion, is preferred from a hardware imple...
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In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new threestep search (NTSS) algorithm if used for low bitrate video coding, as with the H.261 standard. Based on a VLSI tree process...
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ژورنال
عنوان ژورنال: Journal of Real-Time Image Processing
سال: 2013
ISSN: 1861-8200,1861-8219
DOI: 10.1007/s11554-013-0334-5